As clock speeds in circuits continue to increase, circuit board design is becoming increasingly difficult. Ever increasing clock speeds result in ever decreasing slack times which handcuff the designer and limit the flexibility of the design. To compensate, circuit designers use timing analysis tools to reduce development times for circuits with tight timing requirements.
For example, many designers use static timing analysis tools to verify a circuit design. Static timing analysis tools track critical paths through gate level circuitry, typically without regard to the functionality of the circuitry involved. This leads to the traversal and reporting of false critical paths. As a result, the designer who uses static timing analysis tools has to wade through thick timing violation reports only to discover that many of the supposed violations would have never occurred but for the logical operation of the components in a circuit board design. Timing violations, for example, do not occur downstream from a disabled chip. The logical operation of the components in the circuit often interact in a master/slave (controller/controlled) relationship. To investigate all of the supposed violations would require a great deal of time on the part of the engineer. Ignoring potential violations, however, exposes oneself to faulty circuit design. Static timing analysis tools, by their gate level analysis nature, do not handle complex bus functional component-component interactions very well. It is widely known that static timing analysis tools exhibit significant drawbacks when used to analyze the timing of printed circuit boards.
FIGS. 1–3 illustrate a problem with some static analysis tools, which are synchronous. FIG. 1 shows an example of a circuit with two master M1, M2 and two slave S1, S2 components. The output of a master component directly controls the activity of one or more slave components on the bus. A component may be a slave, but behave as a master to other slave components further downstream. A microprocessor, for example, may control a memory controller, which in turn may control one or more banks of memory.
FIG. 2 shows the circuit of FIG. 1 with master M1 and slave S2 active. FIG. 3 shows the circuit of FIG. 1 with master M2 and slave S1 active. For the circuit in FIG. 2, a static timing analysis tool may treat slave S1 as unused circuitry and eliminate it from further analysis. If the state of the circuit then changes to that of FIG. 3, the static timing analysis tool may, having already eliminated slave S1, erroneously treat slave S2 as slave S1.
To overcome problems inherent with static timing analysis tools, some designers have switched to using dynamic timing analysis tools, which consider component operation. Dynamic timing analysis tools generally use a bus functional circuit model. Bus functional means that a component in the circuit is considered at a defined boundary which interacts with other portions of the circuit. The behavior at this boundary is characterized (often as a finite state machine (FSM) with well-defined behavior) to describe the logical operation of the device without exposing un-necessary complexities contained within the internal structure of the component. The internal construction of the integrated circuit is irrelevant, so long as the input/output behavior is well known.
The example problem with static analysis tools given above does not affect dynamic timing analysis tools, because the bus functional circuit model is designed to preserve the integrity of the circuit model. For example, for the circuit in FIG. 2, a dynamic timing analysis tool would simply not make any changes to the slave S1 FSM as long as slave S1 remains inactive. If the state of the circuit then changes to that of FIG. 3, the dynamic timing analysis tool would actively monitor state changes for slave S1, while the slave S2 FSM would stop changing states.
FIG. 4 shows an example of a FSM, in this case representing RAM. The three possible states are IDLE 402, WRITE 404, and READ 406. The RAM state machine changes depending on several inputs including: output enable (OE), chip select (CS), and write enable (WE). For example, when in IDLE 402, the exemplary state machine remains in IDLE 402 as long as CS is high, regardless of OE and WE. The FSM switches from IDLE 402 to READ 406 if WE is high and both CS and OE are low. The FSM switches from IDLE to WRITE if OE is high and both CS and WE are low.
Propagation delays through the RAM may depend on the current state and the next state. For example, it is possible that a transition from the READ 406 state to the WRITE 404 state may take longer than the reverse. The complete behavioral model of a FSM is known as a symbolic model. Symbolic models for use in dynamic timing analysis may be supplied by electronics manufacturers or they may be created by an engineer with a copy of the electronic data sheet for a given integrated circuit. In dynamic timing analysis, also known as symbolic timing analysis, the analysis changes dynamically as simulated behavior of the circuit changes.
Even though dynamic timing analysis tools are far superior to static timing analysis tools, they also suffer from drawbacks. For example, current dynamic timing analysis tools are understood to idealize the behavior of clock signals by using nominal values for propagations delays, which are listed on electronic data sheets.
FIG. 5 shows a circuit with a clock signal that diverges along two paths. Clock 1 terminates a first integrated circuit IC1. Clock 2 propagates through some logic 502 before terminating at a second integrated circuit IC2.
FIG. 6 shows the phase shift 602 in the arrival times of clocks 1 and 2. Clock 2 arrives at IC2 after clock one arrives at IC1, because of the propagation delays of the clock 2 signal that passes through the logic 502. Simulating clock signal propagation with only phase shifts reduces simulation complexity, but can lead to simulation errors due to the oversimplification of clock signal behavior.
Prior art fully functional simulators are understood to idealize clock signals by adding a single value arrival time offset, or phase shift, to a clock signal arrival time at nodes that the clock signal propagates through. Prior art static timing analyzers may return overly pessimistic results, because they are understood to be unable to identify the relational interactions between components either in a clock tree or in the circuit as a whole. Prior art dynamic analysis tools are understood to produce erroneous results in many cases, because the clock tree is reduced to a matrix of phase shift and variance (skew) terms between clock points in the circuit, specifically between “Master” clock points (e.g. drivers) and “Slave” clock points (e.g. receivers). Where the clock points include a portion of the clock tree in common, the phase shift and skew terms are sometimes computed incorrectly by prior art dynamic analysis tools by essentially “double-counting” the delay of the common section. Another problem with current dynamic timing analysis tools as they are understood is in the way they simulate and analyze the circuit.
FIG. 7 shows how current dynamic timing analysis tools are understood to alternate between simulation and analysis. Current dynamic timing analysis tools simulate one clock cycle of circuit behavior and then analyze the simulated circuit behavior for timing violations for that clock cycle. Once the analysis is complete, the simulator picks up where it left off and simulates another clock cycle of circuit behavior, followed by more analysis. The cycle by cycle alternation of the simulator and analyzer continues until the desired timing analysis window has been covered. If the designer wants a simulation/analysis of 20 clock cycles, the prior art dynamic timing analysis tool alternates between the simulator and analyzer 20 times. Unfortunately, this cycle by cycle technique may not verify the timing constraints of some signals, particularly when feedback paths are involved, which may cause some timing errors to be overlooked.
A designer may also choose to use a fully functional simulator, such as ModelSim® simulator software from Mentor Graphics of Willsonville, Oreg., to verify circuit timing. Fully functional simulators commonly use discrete time, simulate circuit behavior at the gate level, and are most commonly used for integrated circuit functionality verification. These simulators typically simulate behavior for thousands or even hundreds of thousands of clock cycles per instance at a large computing cost. In addition, they typically discard timing event information during the simulation, which may be millions of data points per clock cycle. Commonly, only enough data is saved to record functional behavior and for waveform generation to present to the designer. Furthermore, fully functional simulators typically assume that signals arrive at discrete times, because of the massive amount of data generated during analysis. Fully functional simulators also typically require a great deal of interaction from the designer to set up the initial conditions of the simulation.
Fully functional simulators are intended to verify functionality of circuits, and, accordingly, are understood to not generally save complete event data once the event has been simulated and analyzed. The events in functional simulators also do not generally include causality links, nor are they understood to store signal arrival time windows as a range-based simulator does.
Overall, current timing analysis tools suffer from deficiencies when used for bus functional circuit timing analysis, particularly when used for complete system timing verification and generation of routing constraints. Thus, there is a need for an improved timing analysis tool.